The pattern density of an integrated chip (IC) design is a parameter that describes a concentration of a design level (e.g., a metal interconnect layer) within the design. For example, the pattern density of a metal layer within an IC design may be determined by dividing the area of the metal layer by the total area of the design. The pattern density of an IC design is carefully monitored during the design phase of integrated chip development. This is because the pattern density of an IC design impacts corresponding on-wafer structures.
For example, chemical mechanical polishing (CMP) processes used to planarize a substrate are sensitive to the pattern density of the substrate. In areas of the substrate where a pattern density of a metal layer is above the processing specifications of a CMP tool the substrate will dish, resulting in a non-planar substrate that can lead to defects and yield problems.